By Steyaert M. (ed.), van Roermund A.H.M. (ed.), Casier H. (ed.)
Analog Circuit layout includes the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and worthwhile layout rules within the sector of analog circuit layout. each one half is gifted by means of six specialists in that box and cutting-edge info is shared and overviewed. This ebook is quantity 17 during this profitable sequence of Analog Circuit layout.
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Extra info for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
The quadrature output signals of the RO VCO is directly used in the closeby RX and TX modules. The local placement of the RO VCO makes that no clock distribution is needed saving the power for the buffering and avoiding the extra jitter added in this process versus of course the extra power and area requirements of each individual RO VCO in each lane. 44 J. Crols Fig. 7 Layout view of the 2-lane 10 Gbps serdes IP The TX module requires only a differential input clock to drive its serializer, while the RX uses a phase interpolator that runs from a differential quadrature clock input.
With each new step that is taken in the increase of data rates on serial links, the requirements for high frequency jitter generation become stricter. Basically, the generated jitter must scale with the reduction of the bit length. In a typical transmit module the generated random jitter will be mainly determined by the oscillator that generates the clock with which the serializer and line driver is clocked. A ring oscillator is the most practical and lowest cost implementation of an oscillator that can achieve relative high speeds.
25 on average) is converted into +/− 1 by the phase detector. Transient domain simulations show that a low Integral Tracking (It) causes degradation in the high frequency jitter tolerance, thus requiring higher values of Ki. On the other hand, increasing Ki reduces the phase margin in the linear loop model, causing the negative peaking in the jitter tolerance. To improve the phase margin, Kp can be increased, but the overall latency of the digital loop again corrupts the jitter tolerance at high frequency, thus representing the main limitation to the overall CDR performances.
Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management by Steyaert M. (ed.), van Roermund A.H.M. (ed.), Casier H. (ed.)