By Elie Maricau
This ebook specializes in modeling, simulation and research of analog circuit getting older. First, all very important nanometer CMOS actual results leading to circuit unreliability are reviewed. Then, transistor getting older compact versions for circuit simulation are mentioned and several other equipment for effective circuit reliability simulation are defined and in comparison. finally, the influence of transistor getting older on analog circuits is studied. Aging-resilient and aging-immune circuits are pointed out and the impression of know-how scaling is mentioned.
The types and simulation strategies defined within the booklet are meant as an relief for equipment engineers, circuit designers and the EDA neighborhood to appreciate and to mitigate the impression of getting older results on nanometer CMOS ICs.
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Extra info for Analog IC Reliability in Nanometer CMOS
Since device noise determines the minimum detectable signal level, the operation of analog circuits in particular is very prone to these noise sources. Noise is typically modeled as an input-referred noise source, determined from circuit noise analysis and quantified using the noise figure (NF) and signal-to-noise ratio (SNR) parameters. Noise is the ultimate limit to performance in electronic circuits. Electromagnetic Interference Electromagnetic interference (EMI) is defined as the influence of unwanted signals generated by a source circuit and picked up by a receptor or victim circuit, affecting its signal performance and quality.
These sources of variability have a large systematic component. With the aggressive scaling to smaller feature sizes, this component has become larger primarily due to resolution limitations. The inability to scale the wavelength of the light source for lithography has led to an increase of systematic variations, especially in circuit areas with high interconnect and device density (Agarwal and Nassif 2007). To mitigate these problems, a lot of research has gone into more advanced manufacturing flows such as double-patterning technologies (DPT), optical-proximity correction (OPC), extreme ultraviolet lithography (EUVL) and into design techniques such as the use of extremely regular circuit layout (Strojwas 2011).
1986; Pelgrom et al. 1989). Device mismatch became a big issue (especially analog) designers had to deal with in order to guarantee good accuracy and high yield. To overcome scaling limitations of devices fabricated in ultra-scaled CMOS processes, changes in device structures, processing materials and processing conditions have been introduced. These changes have drastically increased the complexity of nanometer CMOS technologies. 0 (Iwai 1999; Bult 2000; Bravaix et al. 2009; Wu et al. 2009; Europractice 2012; International technology roadmap for semiconductors 2011) strained silicon channels to increase the transistor drive current, the introduction of high-k oxides and metal gates to allow further gate oxide scaling combined with reduced gate leakage, and Cu-interconnect with low-k dielectrics to ensure lower RC-delays (Horstmann et al.
Analog IC Reliability in Nanometer CMOS by Elie Maricau